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A multi-phase 10 GHz VCO in CMOS/SOI for 40 Gbits/s SONET OC-768 clock and data recovery circuits

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7 Author(s)
D. Axelrad ; Lab d'Electron. et de Technol. de l'Inf., CEA, Centre d'Etudes Nucleaires de Grenoble, France ; E. de Foucauld ; M. Boasis ; P. Martin
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This paper presents the design of a multi-phase voltage-controlled oscillator (VCO) in CMOS/SOI technology, based on a ring amplifier with LC resonators. This circuit is a key block of a 40 Gbit/s serial communications system. Operating at a speed of one-fourth of the nominal data rate, this CMOS architecture complies with SONET OC-768 standard. The circuit exhibits a 25% frequency tuning range from 10.2 GHz to 13 GHz. The core power dissipation is 26 mW under a -1.2 V supply voltage. The single sideband phase noise measured is better than -104 dBc/Hz, at 1 MHz offset, over the frequency tuning range. The single-ended peak-to-peak amplitude of the four differential signals is 50 mV.

Published in:

2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers

Date of Conference:

12-14 June 2005