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The design of CMOS power amplifiers (PA) is still a challenging issue. Efficiency is one of the key requirements, but it is usually obtained at the expense of large device stress. The latter can be reduced by introducing a cascode solution, which features an efficiency penalty due to dissipative mechanisms associated with MOS capacitive parasitics, overlooked up to date. A class-E PA is proposed which allows simultaneously high efficiency and reduced stress by means of an integrated inductor tuning out the parasitic. Prototypes, realized in a 0.13 μm CMOS technology, demonstrate 67% PAE while delivering 23 dBm peak power at 1.7 GHz. PAE is still above 60% within the range 1.4-2 GHz.