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We demonstrate for the first time that both linearity and efficiency can be optimized for CMOS power amplifiers in the gigahertz range. A technique using large and small transistors in parallel at the output stage for efficiency and linearity enhancement is proposed. A small transistor is used for low power amplification where a larger transistor is turned off to reduce DC power consumption and increase efficiency in the back-off region. The method of improving the linearity of FET amplifiers by offsetting the gate bias to cancel the nonlinearity products is implemented in combination with the efficiency enhancement. For the first time, both techniques are incorporated in the design of a 1.9 GHz CMOS power amplifier that achieves a power-added efficiency (PAE) of 22% at 23-dBm output power. PAE at 6-dB power back-off is measured to be 15%, which exhibits a factor of 2 improvement from the normal class-AB design. Also, third-order intermodulation is improved by approximately 8 dB in the high-power mode of operation when the linearity improvement technique is applied. In addition, this technique does not use transmission line or additional circuits, thus making it ideal for integrated circuit RF power amplifier design.