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Notice of Violation of IEEE Publication Principles
??A sub-Ips rms jitter 1-5GHz 0.13??m CMOS PLL Using a Passive Feedforward Loop Filter with Noiseless Resistor Multiplication??
by Maxim, A.; Gheorghe, M.
in the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2005. Digest of Papers.
After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.
Specifically, the coauthor??s name was fabricated by Adrian Maxim and added to the paper. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:
C. Turinici D. Smith S. Dupue
Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.
Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.
Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A low noise and low spurs multi-GHz PLL frequency synthesizer was realized in a 0.13 μm CMOS process. A fully integrated loop filter was achieved by using a passive feedforward architecture that reduces the on-chip capacitance via a noiseless resistor multiplication. The reference spurs were minimized by using a fast switching charge-pump and a fast reset phase-frequency-detector which provides a dead-zone free operation. Using high PSRR series and shunt regulators to bias the sensitive PLL building blocks, the supply injected spurs were reduced below -65 dBc.
Date of Conference: 14-14 June 2005