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Image processing chain for digital still cameras based on the SIMPil architecture

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4 Author(s)
Gentile, A. ; Dipt. di Ingegneria Informatica, Universita degli studi di Palermo, Italy ; Vitabile, S. ; Verdoscia, L. ; Sorbello, F.

The new generation of wireless devices herald the development of products for integrated portable image and video communication requiring to image and video applications high computing performance. Portable MultiMedia Supercomputers (PMMS), a new class of architectures, allow to combine high computational performance, needed by multimedia applications, and a big energy efficiency, needed by portable devices. Among PMMS, the SIMPil (SIMD processor pixel) architecture satisfies the above requirements, especially with video and digital images processing tasks. In this paper we, exploit the SIMPil computation and throughput efficiency to implement the whole image processing chain of a digital still camera device. The implemented chain covers the whole image pipeline: from the Bayer pattern image processing to the JPEG image compression. SIMPil performance has been evaluated using an instruction level simulator. To prove the effectiveness of the proposed approach, processing and compression results have been compared with the Texas Instruments Inc. TMS320C549 DSP one.

Published in:

Parallel Processing, 2005. ICPP 2005 Workshops. International Conference Workshops on

Date of Conference:

14-17 June 2005

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