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Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process

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4 Author(s)
Dyer, T. ; National Semicond. (UK) Ltd., Greenock, UK ; McGinty, J. ; Strachan, A. ; Bulucea, C.

The monolithic integration of trench vertical DMOS (VDMOS) n-channel transistors into an IC BCD process is reported for the first time. The integration scheme for the trench VDMOS module is discussed and silicon results are compared with TCAD simulations. For a 50-V device, the integrated trench device is shown to offer at least a factor-of-two RDS(ON) × area advantage over its planar counterpart. An RDS(ON) × area value of 80 mΩmm2 is achieved for the integrated trench VDMOS using a minimum feature size of 1 μm.

Published in:

Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD '05. The 17th International Symposium on

Date of Conference:

23-26 May 2005

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