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On-chip high voltage charge pump in standard low voltage CMOS process

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3 Author(s)
Hasan, T. ; Dept of Eng., Univ. of Cambridge, UK ; Lehmann, T. ; Kwok, C.Y.

An on-chip high voltage tolerant 4VDD charge pump with symmetrical architecture in a standard low voltage 1.8 V 0.18 μm CMOS process is presented. For a 250 kΩ load, circuit efficiency of the charge pump is approximately 71%. All the MOS transistors satisfy typical voltage stress related reliability requirements for standard low voltage CMOS devices.

Published in:

Electronics Letters  (Volume:41 ,  Issue: 15 )