By Topic

The selective read-out processor for the CMS electromagnetic calorimeter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)

This paper describes the selective read-out processor (SRP) proposed for the electromagnetic calorimeter (ECAL) of the Compact Muon Solenoid (CMS) experiment at LHC (CERN). The aim is to reduce raw ECAL data to a level acceptable by the CMS data acquisition (DAQ) system. For each positive level 1 trigger, the SRP is guided by trigger primitive generation electronics to identify ECAL regions with energy deposition satisfying certain programmable criteria. It then directs the ECAL read-out electronics to apply predefined zero suppression levels to the crystal data, depending whether the crystals fall within these regions or not. The main challenges for the SRP are some 200 high speed (1.6 Gbit/s) I/O channels, asynchronous operation at up to 100 kHz level 1 trigger rate, a 5-μs real-time latency requirement and a need to retain flexibility in choice of selection algorithms. The architecture adopted for the SRP is based on modern parallel optic pluggable modules and high density field programmable gate array (FPGA) devices with embedded processors and multigigabit transceivers. Implementation studies to validate proposed solutions are presented. The performance of envisaged selection algorithms is investigated with the CMS detector simulation software. The robustness of optical communication channels is estimated via direct measurements and calculations. The feasibility to perform data reduction operations within the allocated timing budget is verified by running a representative SRP firmware on a development board with a Xilinx Virtex2Pro FPGA device.

Published in:

IEEE Transactions on Nuclear Science  (Volume:52 ,  Issue: 3 )