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High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz

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2 Author(s)
U. Singh ; Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Irvine, CA, USA ; M. M. Green

The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations of these circuits in a 0.13-μm CMOS process show a significant improvement in high-frequency operation compared to a conventional D flip-flop-based divider. Measured sensitivity curves of these dividers give maximum frequency of operation ranging from 20 to 38 GHz with power consumption of 12 mW from a 1.8-V supply voltage.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:40 ,  Issue: 8 )