Referenced Items are not available for this document.
We describe a high-performance fully ion-implanted planar InP junction FET fabricated by a shallow (4000-Å) n-channel implant, an n+source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000-Å) abrupt p-n junction, followed by a rapid thermal activation. From FET's with gates 2 µm long, a transconductance of 50 mS/mm and an output impedance of 400 Ω.mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The FET has a threshold voltage of -2.4 V, and a saturated drain current of 60 mA/mm at V
Published in:
Electron Device Letters, IEEE
(Volume:8
,
Issue:
11
)
Date of Publication: Nov 1987
- Page(s):
- 518 - 520
- ISSN :
- 0741-3106
- Digital Object Identifier :
- 10.1109/EDL.1987.26714
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 09 August 2005
- Issue Date :
- Nov 1987
- Sponsored by :
- IEEE Electron Devices Society
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