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A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's

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6 Author(s)
Kim, S.J. ; AT&T Bell Laboratories, Murray Hill, NJ ; Wang, K.W. ; Vella-Coleiro, G.P. ; Lutze, J.W.
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We describe a high-performance fully ion-implanted planar InP junction FET fabricated by a shallow (4000-Å) n-channel implant, an n+source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000-Å) abrupt p-n junction, followed by a rapid thermal activation. From FET's with gates 2 µm long, a transconductance of 50 mS/mm and an output impedance of 400 Ω.mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The FET has a threshold voltage of -2.4 V, and a saturated drain current of 60 mA/mm at Vgs= 0 V with negligible drift.

Published in:

Electron Device Letters, IEEE  (Volume:8 ,  Issue: 11 )

Date of Publication:

Nov 1987

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