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N-source/drain compensation effects in submicrometer LDD MOS devices

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4 Author(s)
Hamada, A. ; Hitachi Ltd., Tokyo, Japan ; Igura, Yasuo ; Izawa, Ryuichi ; Takeda, E.

N- source/drain compensation effects in LDD devices and p-n junction leakage effects are investigated. In particular, for L_{eff} \leq 0.3 µm, these effects will become intrinsic constraints on device minituarization. Furthermore, p-n junction leakage was found to cause refresh failures in dynamic VLSI circuits even under reduced power supply voltage.

Published in:

Electron Device Letters, IEEE  (Volume:8 ,  Issue: 9 )