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Radiation-hardened silicon-on-insulator junction field-effect transistors fabricated by a self-aligned process

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3 Author(s)
Choi, H.K. ; Massachusetts Institute of Technology, Lexington, MA ; Tsaur, B.-Y. ; Chen, C.K.

A self-aligned process has been developed for fabricating JFET's in zone-melting-recrystallized (ZMR) Si films on SiO2-coated Si substrates. This process has been used to fabricate n-JFET's exhibiting transconductance values up to 63 mS/mm. For 228 devices within an area of about 4 × 4 cm2, the mean threshold voltage is 578 mV and the standard deviation is 22 mV. With a -15-V bias applied to the Si substrate during irradiation and device operation, the devices show low threshold voltage shift (< -75 mV) and small transconductance degradation (∼30 percent) for exposure to total-dose radiation of 108rad(Si).

Published in:

Electron Device Letters, IEEE  (Volume:8 ,  Issue: 3 )

Date of Publication:

Mar 1987

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