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This paper describes the performance of an optimally designed virtual-phase frame-transfer CCD image sensor having 774H × 488V elements and an 8-mm diagonal for the image-sensing area. The sensor employs electron-hole recombination antiblooming and achieves high performance by both maximizing the well capacity and reducing the reset noise using an on-chip correlated clamp sample and hold signal processing technique. The imager conforms to the NTSC standard and is intended for color camera applications. The details described include processing modifications, circuit optimization for maximum signal-to-noise performance, and various layout illustrations with emphasis on the design of the three serial registers that multiplex the signals into the three individual outputs. The minimal driving requirements characteristic of the virtual-phase CCD device have been preserved by interconnecting the serial registers with the gates of signal-processing transistors and by applying timing pulses that clock the registers as well as provide the appropriate signal-processing functions. Discussions presented in the paper are focused on comparisons of theoretical predictions of maximum attainable performance with measured results.