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Analysis and modeling of floating-gate EEPROM cells

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4 Author(s)
Kolodny, A. ; Intel Israel Design Center, Haifa, Israel ; Nieh, S.T.K. ; Eitan, B. ; Shappir, J.

Floating-gate MOS devices using thin tunnel oxide are becoming an acceptable standard in electrically erasable nonvolatile memory. Theoretical and experimental analysis of WRITE/ERASE characteristics for this type of memory cell are presented. A simplified device model is given based on the concept of coupling ratios. The WRITE operation is adequately represented by the simplified model. The ERASE operation is complicated due to formation of depletion layers in the transistor's channel and under the tunnel oxide. Experimental investigation of these effects is described, and they are included in a detailed cell model. In certain cell structures, a hole current can flow from the drain into the substrate during the ERASE oepration. This effect is shown to be associated with positive charge trapping in the tunnel oxide and threshold window opening. An experimental investigation of these phenomena is described, and a recommendation is made to avoid them by an appropriate cell design.

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Electron Devices, IEEE Transactions on  (Volume:33 ,  Issue: 6 )