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A highly latchup-immune 1 µm CMOS technology fabricated with 1 MeV ion implantation and self-aligned TiSi2

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10 Author(s)
Lai, F.S. ; IBM General Products Division, San Jose, California ; Wang, L.K. ; Taur, Y. ; Sun, Y.C.
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A 1 µm n-well CMOS technology with high latchup immunity is designed, realized, and characterized. The main features of this technology are : 1 MeV ion-implanted retrograde n-well, buried contact, arsenic-phosphorous double diffused n+/n-junction, self-aligned TiSi2on gate and diffusions with nitride spacer, and thin p epi on p+substrate. This technology has been demonstrated via the successful fabrication of high-performance 64K CMOS SRAM chips. It is also observed that the silicide plays an important role in latchup prevention since it reduces the emitter efficiencies of parasitic bipolar devices.

Published in:

Electron Devices Meeting, 1985 International

Date of Conference:

1-4 Dec. 1985