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Latchup-free CMOS structure using shallow trench isolation

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7 Author(s)
Y. Niitsu ; Toshiba Corporation, Kawasaki, Japan ; S. Taguchi ; K. Shibata ; H. Fuji
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Using a shallow trench and a thin epitaxial layer, latchup-free CMOS has been realized. When the trench depth is 1.4 µm and the epitaxial layer thickness is 2 µm, the latchup holding voltage, VHis higher than 13 V. The mechanism of VHincrease is discussed using an equivalent circuit including the reverse transistors of the parasitic bipolar transistors. The interruption of lateral current flow with the trench contributes to VHincrease. From the results, it is well expected that the only about 1 µm deep trench must be adequate for achieving VHhigher than the supply voltage, i.e. 5V, and that the fabrication process of trench isolation becomes more reliable and easier.

Published in:

Electron Devices Meeting, 1985 International  (Volume:31 )

Date of Conference:

1985