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Monolithic integration of a planar embedded InGaAs p-i-n detector with InP depletion-mode FET's

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7 Author(s)
Tell, B. ; AT&T Bell Laboratories, Homedell, NJ ; Liao, Andrew S.H. ; Brown-Goebeler, K.F. ; Bridges, T.
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We report the operation of a fully integrated p-i-n FET circuit based on a planar embedded In0.53Ga0.47As p-i-n detector and load resistor with InP depletion-mode FET's. The structure employs selective growth of InGaAs on a semi-insulating InP substrate and selective ion implantation of Si and Be into the InP and InGaAs, respectively. For a 10-9bit error rate at 1.54 m, the circuit achieves a sensitivity of -34 dBm at 90 Mbit/s and -29.5 dBm at 295 Mbit/s.

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Electron Devices, IEEE Transactions on  (Volume:32 ,  Issue: 11 )