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VLSI for high-performance graphic control utilizing multiprocessor architecture

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4 Author(s)
K. Katsura ; Hitachi-shi Ltd., Ibaraki-ken, Japan ; H. Maejima ; K. Minorikawa ; H. Yonezawa

This paper describes the VLSI for high-performance graphic control which utilizes two-level multiprocessor architecture. The VLSI chip is constructed of multiprocessor modules processing in parallel, and each processor module is constructed of multiexecutors using pipeline processing. This dedicated VLSI chip, designated as advanced CRT controller (ACRTC), has three processor modules, each independently controlling drawing, display, and timing. The graphic architecture of the drawing processor, which controls graphic drawing, is described. A high-level graphic language based on an X-Y coordinate system is adopted. High-speed drawing is realized (drawing rate is 500 ns/pixel for drawing a line) by pipeline processing with three executors, the logical address executor, physical address executor, and color data executor.

Published in:

IEEE Transactions on Electron Devices  (Volume:32 ,  Issue: 11 )