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A fully scaled submicrometer NMOS technology using direct-write E-beam lithography

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5 Author(s)
Wordeman, M.R. ; IBM Thomas J. Watson Research Center, Yorktown Heights, NY ; Schweighart, A.M. ; Dennard, R.H. ; Sai-Halasz, G.
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Fully scaled NMOS devices, circuits, and dynamic memory with 1/2-µm nominal minimum dimensions at each level have been fabricated using direct-write e-beam patterning. This high-density NMOS technology yields nominally loaded average gate delays of 650 ps/stage with a power dissipation of 38 µW. The characteristics of this technology are presented with specific emphasis placed on features of the design which are unique to submicrometer MOSFET's, including a study of nonscaling effects and their impact on the device and circuit design.

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Electron Devices, IEEE Transactions on  (Volume:32 ,  Issue: 11 )