Optimum design of dual-control gate cell for high-density EEPROM's

A new floating-gate-type cell with a dual-control gate (dc cell) has been developed and the structure optimized to realize high-density EEPROM's. In this new cell, an address selection transistor has been eliminated, thus attaining a single-transistor-per-cell configuration. The address selection is achieved by coincidence of two control gates, which are connected to column or row decoders supplied with an appropriate programming voltage. The stored charge in the floating gate suffers some disturbance by repetition of half-selection mode operation--defined as a state in which one of the control gates is set to high and the other to low during programming. In order to improve the endurance of the cell against half-selection mode operation, a new source biasing method has been introduced. As a result, the endurance has been improved by more than 3 orders of magnitude. A WRITE/ERASE endurance of 10
⁵
cycles and a data retention capability of more than 10 years have been obtained for the dc cell. The design parameters for a 64K EEPROM chip are also described.