Shallow p+-n junctions in silicon are fabricated by the implantation of 10 keV B+or 50 keV BF2+ions at a fluence of 3 × 1015/ cm2through a capping layer of 25-nm SiO2. Sheet resistance, contact resistivity, and forward and reverse bias leakage current are measured for various furnace and rapid thermal annealing (RTA) conditions. SIMS profiles are included. RTA allows the simultaneous achievement of junctions with j < 4 nA/cm2, , and . cm2for junction depths of the order of 0.25 µm as mesured by the traditional bevel-and-strain method.