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Two techniques are described which serve to minimize the problem of slow Newton convergence and, at times, divergence sometimes experienced in applying this iterative technique to the solution of nonlinear semiconductor equations. The truncated correction method limits the wide excursions in the solution parameters which can occur during the Newton iterative procedure and thereby permits fewer voltage increments to be used in applying large bias voltages (1000 V)in simulating semiconductor power device operation. The doping-incrementation method uses the technique of gradually incrementing the doping levels in the heavily doped regions in a device structure to provide better solution first guesses in the simulation of devices containing such regions. Substantial savings in computer time are obtained in applying these two numerical procedures.