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An advanced design method integrating different design approaches is proposed which can attain an optimized chip design within an acceptable turnaround time (TAT). Logic VLSI networks can be generally partitioned into data path logic, control logic, and on-chip memories. The data path logic is primarily realized by using repeatable structured general purpose function blocks, while the control logic is designed using standard cells or programmable logic arrays (PLA's), A cell library and powerful CAD programs are utilized to shorten the TAT. A CMOS 16-bit micro-computer is designed with this approach and compared with a fully automated standard cell chip. A gate density improvement of 30 percent is observed. A design effort of only 20 man-months is achieved.