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NMOS Process integration for a 1m word × 1 bit DRAM

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8 Author(s)
Shibata, T. ; Toshiba Corporation, Kawasaki, Japan ; Moriya, T. ; Kurosawa, K. ; Mitsuno, T.
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The standard two-level polysilicon NMOS technologies have been integrated to fabricate a 1 Mbit DRAM. A large storage capacitance has been realized by maximizing the storage area using BOX (Buried Oxide) isolation. A novel two-level aluminum metallization process has been incorporated for reducing the word-line resistance as well as facilitating the peripheral circuit layout. The optimum design of basic LDD transistors was performed based on the concept of critical channel length, experimentally determined minimum safety channel length for hot-electron induced degradation.

Published in:

Electron Devices Meeting, 1984 International

Date of Conference:

9-12 Dec. 1984