Referenced Items are not available for this document.
Fault simulation of VLSI circuits takes considerable computing resources and there have been significant efforts to speed up the fault simulation process. A distributed fault simulator implemented on a loosely-coupled network of general-purpose computers is described. The techniques used result in a close to linear speedup and can be used effectively in most industrial VLSI CAD (computer-aided design) environments.<
Published in:
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Date of Conference: 12-15 June 1988
- Page(s):
- 686 - 691
- Meeting Date :
- 12 Jun 1988-15 Jun 1988
- ISSN :
- 0738-100X
- Print ISBN:
- 0-8186-0864-1
- INSPEC Accession Number:
- 3257882
- Conference Location :
- Anaheim, CA, USA
- Digital Object Identifier :
- 10.1109/DAC.1988.14843
- Product Type:
- Conference Publications
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