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A three-dimensional CMOS design methodology

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3 Author(s)
Hoefflinger, Bernd ; Purdue University, West Lafayette, IN ; Liu, S.T. ; Vajdic, B.

A technology-updatable design methodology for three-dimensional (3-D) CMOS circuits has been developed. Four levels of abstraction have been implemented with topographical congruence: 1) technology level, 2) mask level, 3) transistor level, and 4) logic level. A novel transistor level symbolic representation is introduced which emphasizes the three-dimensional nature of the circuits. A number of design examples is presented.

Published in:

Electron Devices, IEEE Transactions on  (Volume:31 ,  Issue: 2 )