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A 1.0 µm N-well CMOS/Bipolar technology for VLSI circuits

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6 Author(s)
Miyamoto, J. ; Toshiba Corporation, Kawasaki, Japan ; Saitoh, S. ; Momose, H. ; Shibata, H.
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This paper describes a 1.0um N-well CMOS/bipolar technology for VLSI analog-digital combined VLSI systems. With this technology, high performance CMOS and collector isolated NPN transistors can be implemented on the same chip. By comparing and analyzing the characteristics of ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors without buried layer, it was concluded that CMOS is more suitable for digital parts ,while bipolar is superior for analog parts. Concerning the bipolar input/output buffers, the patterned buried layer is required in order to improve the drivability and the high frequency response. The technology was successfully applied to a motive device, a high-speed static RAM, and improvement in access time was verified.

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Electron Devices Meeting, 1983 International

Date of Conference:

5-7 Dec. 1983