By Topic

Hole current in dual dielectric under positive gate voltage

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yau, L.D. ; Intel Corporation, Aloha, OR ; Liou, F.-T. ; Chen, S.

n-channel dual-dielectric transistors with SiO2:Si3N4gate insulators were fabricated with and without boron implant in the channel. Under positive gate voltage stress, electrons can enter the insulator from the silicon, and holes can enter the silicon from the insulator. The electrons and holes were measured by the technique described by Ginovker et al.[1]. For oxides thicker than 30 Å, it is always observed that the silicon hole current is 3-4 orders of magnitude below the silicon electron current. The physical origin of this hole current is shown to be field-enhanced excitation of electrons from the valence band to the conduction band in the silicon prior to entering the insulator, and is not due to the holes from the insulator entering the silicon.

Published in:

Electron Device Letters, IEEE  (Volume:4 ,  Issue: 8 )