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Determination of the spatial variation of interface trapped charge using short-channel MOSFET's

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3 Author(s)
Russell, T.J. ; National Bureau of Standards, Washington, DC ; Wilson, C.L. ; Gaitan, M.

Previous measurements of interface trapped charge (ITC) by charge pumping used long-channel metal gate transistors. In this paper charge pumping is extended to short-channel Self-aligned polysilicon gate transistors and used to determine the spatial variation of ITC on wafers. Only the MOSFET gate area and a pulse frequency are required to calculate ITC density from the charge pumping current. In previous work, with long-channel devices, it appears that some investigators used the design dimension of metal gate devices and others used the metallurgical channel length of the transistors to calculate gate area. Two-dimensional simulation of the charge pumping measurement showed that, for a sufficient applied pulse height voltage, the correct area is obtained if the polysilicon gate length and width asmeasured are used. When the process-induced variation of the polysilicon gate length is included in the measurement analysis, no systematic variation of ITC is observed across 5 cm wafers. The charge pumping measurement technique on short-channel MOSFET's can be used to resolve the spatial variation of ITC if the area variations are correctly handled. The measurement of ITC is linear with frequency from 1 kHz to 1 MHz, indicating that the emission time constant of the fast states measured using this method is ≤10-6s. A variation of ITC with channel lengths is also observed. This variation could not be detected using large area devices such as capacitors, but will have important consequences for short-channel MOSFET's.

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Electron Devices, IEEE Transactions on  (Volume:30 ,  Issue: 12 )