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PLA design for single-clock CMOS

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1 Author(s)
Blair, Gerard M ; Dept. of Electr. Eng., Edinburgh Univ., UK

The circuit implementation of a CMOS programmable logic array (PLA) is described for use with a single-phased clock, combining both dynamic and pseudo-NMOS design styles. Compact layout and high speed of operation is achieved with low static power dissipation. The circuit design, circuit speed, circuit layout, and timing diagram are presented

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 8 )