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An offset reduction technique for use with CMOS integrated comparators and amplifiers

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2 Author(s)
J. H. Atherton ; Siemens Corporate Res. Inc., Princeton, NJ, USA ; H. T. Simmonds

Methods for reducing the input offset voltage of comparators and amplifiers are reviewed. A comparator that adjusts its own offset either at power-up or in response to a control input is presented. The nature of the offset adjustment is such that the comparator is capable of continuous-time operation. Room-temperature offset in the range of -100 to +100 μV are achievable. Adjusted offsets exhibit a temperature coefficient on the order of -1 μV/°C

Published in:

IEEE Journal of Solid-State Circuits  (Volume:27 ,  Issue: 8 )