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An analytical access time model for on-chip cache memories

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3 Author(s)
T. Wada ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; S. Rajan ; S. A. Przybylski

An analytical access time model for on-chip cache memories that shows the dependence of the cache access time on the cache parameters is described. The model includes general cache parameters, such as cache size (C), block size (B), and associativity (A), and array configuration parameters that are responsible for determining the subarray aspect ratio and the number of subarrays. With this model, a large cache design space can be covered, which cannot be done using only SPICE circuit simulation within a limited time. Using the model, it is shown that for given C, B, and A , optimum array configuration parameters can be used to minimize the access time; if the optimum array parameters are used, then the optimum access time is roughly proportional to the log (cache size), and when the optimum array parameters are used, larger block size gives smaller access time, but larger associativity does not give smaller access time because of the increase of the data-bus capacitances

Published in:

IEEE Journal of Solid-State Circuits  (Volume:27 ,  Issue: 8 )