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A secondary cache controller design for a high-end microprocessor

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1 Author(s)
Lee, Y.S. ; Intel Corp., Santa Clara, CA, USA

The design of a CMOS cache controller chip for a high-end (i486) microprocessor is presented. The cache controller supports either two lines per tag (sectored) or one line per tag (nonsectored). A single cache controller directly supports nonsectored 64 kilobyte or sectored 128 kilobyte cache memories. The sectored mode effectively doubles the cache size compared to the nonsectored mode while maintaining the same tag RAM size. The cache controller is designed to be completely software transparent and contains a 4 K-tag entry tag RAM on-chip and supports burst read, burst line fill, snoop, and back-off cycles. Read-only spaces can also be cached with write protections. Two-way set associativity, sectored cache, and efficient cache protocols optimize performance of the cache memory system and complexity of the cache controller design. This chip supports a 25- or 33-MHz microprocessor. This high speed is achieved by dividing the tag RAM array into eight small sections, thus reducing the overall access time of the tag RAM

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 8 )