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Memory-cell design in Josephson technology

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1 Author(s)
H. H. Zappe ; IBM Thomas J. Watson Research Center, Yorktown Heights, NY

Operating principles and criteria for the design of Josephson memory cells are reviewed and the evolution of cell design is retraced to highlight the various constraints imposed by the requirement for high speed, density, large Operating margins, and ease of auxiliary memory circuit design. Two attractive cells have emerged so far. One is a nondestructive readout (NDRO) ring cell for a subnanosecond cache memory chip; the other a destructive readout (DRO) single-flux quantum cell for main memory applications. Both are presently being used as the basis for ongoing design work.

Published in:

IEEE Transactions on Electron Devices  (Volume:27 ,  Issue: 10 )