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In VLSI fabrication, electron-beam systems are increasingly being used to expose a submicrometer pattern directly on the wafer. The authors have already presented the electron-beam lithography system called AMDES. This paper mainly discusses the computer-controlled advanced-proximity-effect correction and warped-wafer-correction functions of that system. The authors suggest advanced-proximity-effect correction techniques, a pattern-shape adjustment technique, a variety of pattern-shape modification techniques, a dotbeam correction method, and a simultaneous-calculation technique based on a consideration of the symmetry of paired patterns. A computational exposure-dose distribution model for rectangular-shaped beams is also discussed. Warped-wafer correction is necessary since the process-induced warpage distortion produces limitations in multi-level pattern alignment. This paper clarifies the necessary and sufficient conditions for determining the minimum number of registration marks needed to guarantee an acceptable error for a given design-pattern size.