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Selective ion implantation to reduce power consumption in MOS integrated circuits

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2 Author(s)
Ahmed, H. ; Cambridge University, Cambridge, England ; Charpentier, A.

A method of using implantation to reducek'in selected MOS transistors on an LSI chip is described. An application of this technique is described where the power consumed in circuits such as memory cells is reduced without impairing other operating parameters.

Published in:

Electron Devices, IEEE Transactions on  (Volume:25 ,  Issue: 5 )

Date of Publication:

May 1978

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