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Digital filter and square timing recovery

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2 Author(s)
M. Oerder ; Lehrstuhl fuer Elektrische Regeleungstechnik, Aachen Univ. of Technol., West Germany ; H. Meyr

The digital realization of timing recovery circuits for digital data transmission is considered. A digital algorithm is proposed that can be implemented very efficiently even at high data rates. The resulting timing jitter has been computed and verified by simulations. In contrast to other known algorithms, the one presented here allows free-running sampling oscillators and a novel planar filtering method that prevents synchronization hangups

Published in:

IEEE Transactions on Communications  (Volume:36 ,  Issue: 5 )