P-channel enhancement mode MOS field effect transistors have been fabricated on high resistivity P-type (π) silicon substrates. A high off-state impedance can be achieved with zero gate voltage if the substrate resistivity is sufficiently high so that the P+π low-high junctions formed by the diffusion of the drain and source regions exhibit the desired rectifying characteristics. N-channel MOSFETs can also be fabricated on these high resistivity π substrates. While the N-channel devices usually exhibit depletion mode characteristics, both N and P-channel enhancement type MOSFETs can be simultaneously fabricated on a signal substrate if Al2O3-SiO2gate insulating layers are used and if QSSis kept sufficiently small. The channel lengths must be sufficiently large to eliminate SCL current flow from drain to source with zero gate voltage. Off-state leakage currents on the order of nanoamperes have been observed for both units when the channel length was equal to 2 mils. By using techniques such as beam-lead interconnections or dielectric. isolation, complementary MOS integrated circuits can be fabricated on a single substrate and only two diffusions are required. Additional advantages of this approach include: extremely high carrier mobilities, very low threshold voltages for both units and negligible variation of MOSFET charac teristics with reverse substrate bias.