Cart (Loading....) | Create Account
Close category search window

A comparison of MOS varactors in fully-integrated CMOS LC VCO's at 5 and 7 GHz

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ainspan, H. ; IBM T. J. Watson Research Center, Yorktown Heights, N.Y. ; Plouchart, J.-O.

This paper examines the effect of the choice of MOS varactor on the performance of a CMOS negative resistance oscillator. The three most common MOS varactor structures (inversion, accumulation, and gated varactor) are combined with a spiral inductor over either deep trench oxide or a polysilicon patterned ground shield, to implement a matrix of six LC VCO's in a 0.24-µm (0.18- µm Leff) SiGe BiCMOS technology[1]. Typical measured VCO phase noise is -119.7 dBc/Hz at a 1-MHz offset from a 5.67-GHz carrier, while drawing 1.6 mA from a 1.5-V supply, for a VCO figure of merit of-191 dBc/Hz.

Published in:

Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European

Date of Conference:

19-21 Sept. 2000

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.