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Dynamically programmable parallel processor (DPPP): A novel reconfigurable architecture with simple program interface

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4 Author(s)

Routing flexibility is often the dominant issue in many reconfigurable devices, especially devices with fine granularity such as FPGA. This paper describes a new architecture-based reconfigurable device, Dynamically Programmable Parallel Processor (DPPP) which utilises a multiple access bus. DPPP is designed to provide 100% routing flexibility and to achieve high parallelism. DPPP also features its programmability as it can be simply compiled by using numerical formulas as input. A prototype chip based on the proposed architecture had been implemented into a 4.5mm×4.5mm chip with 0.6mm CMOS process.

Published in:

Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European

Date of Conference:

19-21 Sept. 2000