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Measurements and analysis of PLL jitter caused by digital switching noise

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1 Author(s)
Larsson, P. ; Bell Labs, Lucent Technologies, Holmdel, NJ

Substrate coupling between a noise-generating digital circuit and analog PLL's realized in a standard low-resistivity substrate 0.25µm CMOS process is analyzed. It is found that the main source of jitter strongly depends on the power supply configuration of the PLL.

Published in:

Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European

Date of Conference:

19-21 Sept. 2000