By Topic

A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM wireless receivers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
W. S. -T. Yan ; Hong Kong University of Science and Technology, Kowloon, Hong Kong ; H. C. Luong

A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.5-mm CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm2and consumes a low power of 34 mW. The measured phase noise of the dual-loop synthesizer is -121.8 dBc/Hz at 600-kHz frequency offset. The measured spurious levels are -79.5 and -82 dBc at 1.6 MHz and 11.3MHz offset, respectively.

Published in:

Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European

Date of Conference:

19-21 Sept. 2000