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A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM wireless receivers

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2 Author(s)
Yan, W.S.-T. ; Hong Kong University of Science and Technology, Kowloon, Hong Kong ; Luong, H.C.

A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.5-mm CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm2and consumes a low power of 34 mW. The measured phase noise of the dual-loop synthesizer is -121.8 dBc/Hz at 600-kHz frequency offset. The measured spurious levels are -79.5 and -82 dBc at 1.6 MHz and 11.3MHz offset, respectively.

Published in:

Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European

Date of Conference:

19-21 Sept. 2000