A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM wireless receivers

A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.5-mm CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm
²
and consumes a low power of 34 mW. The measured phase noise of the dual-loop synthesizer is -121.8 dBc/Hz at 600-kHz frequency offset. The measured spurious levels are -79.5 and -82 dBc at 1.6 MHz and 11.3MHz offset, respectively.