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A Vector Unit (VU) for the high performance 3D graphics computing has been developed. Four fMAC (floating-point Multiply-Accumulate) units which execute multiply-add operation with one throughput, one fDIV (floating-point Divide) unit which executes division and square root operations with 6 cycles at 300 MHz and 128 bits × 32 words fReg (floating-point register file) are implemented. This architecture delivers a peak performance of 2.44 GFLOPS at 300MHz.
Date of Conference: 21-23 Sept. 1999