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Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques for 2-3GHz on-chip cache arrays in microprocessors on 90nm logic technology

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11 Author(s)
Khellah, M. ; Circuits Res., Intel, Hillsboro, OR, USA ; Yibin Ye ; Somasekhar, D. ; Casper, D.
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Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques, implemented for cache arrays on a testchip in a 90nm logic technology, demonstrate improvement in operational frequency from 1.2GHz to 2GHz for BLC, and to 3GHz for BLR, with 17% and 10% area impacts, respectively.

Published in:
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference: 16-18 June 2005

Page(s):
262 - 263
Print ISBN:
4-900784-01-X
INSPEC Accession Number:
8573503
Digital Object Identifier :
10.1109/VLSIC.2005.1469381
Product Type:
Conference Publications

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