Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques for 2-3GHz on-chip cache arrays in microprocessors on 90nm logic technology

Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques, implemented for cache arrays on a testchip in a 90nm logic technology, demonstrate improvement in operational frequency from 1.2GHz to 2GHz for BLC, and to 3GHz for BLR, with 17% and 10% area impacts, respectively.