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A self-tuning DVS processor using delay-error detection and correction

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8 Author(s)
Das, S. ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; Pant, S. ; Roberts, D. ; Seokwoo Lee
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In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18μm technology. The processor employs delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44% energy savings over the worst case operating conditions for a 0.1 % targeted error rate at a fixed frequency of 120MHz.

Published in:

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference:

16-18 June 2005