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A 1V supply 50nV/√Hz noise PSD CMOS amplifier using noise reduction technique of autozeroing and chopper stabilization

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5 Author(s)
Yoshida, T. ; Graduate Sch. of Adv. Sci. of Matter, Hiroshima Univ., Japan ; Masui, Y. ; Mashimo, T. ; Sasaki, M.
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A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched op-amp. The low-noise amplifier fabricated in a 0.18-μm CMOS technology achieved 50-nV/VHz input noise at 1-MHz chopping and 0.5-mW power consumption at 1-V supply voltage.

Published in:

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference:

16-18 June 2005