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A design methodology is presented for low power distributed amplifiers and is used for the design of a 9 mW LNA with programmable gain implemented in a 0.18 μm CMOS process. The LNA provides a gain of 8 ± 0.6 dB from DC to 6.2 GHz, with an input match of -16 dB and an output match of -10 dB over the entire band. The IIP3 is +1.8 dBm, and the NF ranges from 4.2 to 6.2 dB. The gain is tunable from -10 dB to +8 dB while gain flatness and matching are maintained.