Skip to Main Content
A 2.0V, 256Mbit packet-based DRAM with bandwidth of 10GB/s (5.0Gbps × 16pin) was fabricated. To have high data bandwidth and stable clock generation, high performance input receiver and process insensitive PLL bias scheme were used. To increase the write speed of the cell array, write without 10 pre-charge scheme was employed. The power consumption and area of the chip are 2.4W and 7.2×10.2mm2 respectively.