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An area-efficient PLL architecture in 90-nm CMOS

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1 Author(s)
Lim, P.J. ; Nvidia Corp., Santa Clara, CA, USA

An area-efficient phase-locked loop (PLL) design is presented. The PLL architecture allows the implementation of a charge-pump based PLL stabilization filter network using sample-reset techniques and a total loop-capacitor equivalent to a typical ripple-reduction capacitor. Implemented in a logic 90-nm CMOS process, this PLL integrates a total loop capacitance of 3 pF using parasitic metal-metal capacitor structures, measures 160 × 171 μm and exhibits a measured rms period jitter of 1.68 ps at 2.5 GHz.

Published in:

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference:

16-18 June 2005