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The circuits and physical design of the synergistic processor element of a CELL processor

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14 Author(s)
Takahashi, O. ; IBM Syst. & Technol. Group, Austin, TX, USA ; Cook, R. ; Cottier, S. ; Dhong, S.H.
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A 32b 4-way SIMD dual-issue synergistic processor element of a CELL processor is developed with 20.9 million transistors in 14.8mm2 using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the non-SRAM area. ISA, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power efficient design. Correct operation has been observed up to 5.6GHz at 1.4V supply and 56°C.

Published in:

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference:

16-18 June 2005